ASIC/FPGA Design Engineer |Gold Medalist | Good analytical and algorithmic thinking skills.

Bhagesh's CV

BHAGESH CHOUDHRY MAHESHWARI

28 Woodlawn Park Ave Tymon South

Dublin 24 D24 Y02N.
Phone: (+353) (concealed information)/ (+92) (concealed information)
Email: (concealed information)

Summary

A technology enthusiast and skilled engineer with versatile technical and managerial skills gained through academics and projects, participation and organization of national level events/competitions and from the international experience of working as Cultural ambassador in USA and as intern in CERN, Switzerland, the largest particle accelerator in the World.


WORK EXPERIENCE

• Digital ASIC Design Engineer -2, Xilinx Ireland (Sept 2019- Present)


* Digital IP Design Engineer, Cypress Semiconductors Ireland (May 2018- August 2019)
Being an IP design engineer I worked on multiple aspects of IP development. These include Verilog based RTL development, linting, CDC, synthesis, formal equivalence checking, DFT/scan insertion, ATPG coverage estimation and basic STA analysis. During this experience I worked on blocks based on AXI protocol and to be used in automotive systems.

• Computing labs Assistant, Technological University Dublin (Jan-2017 – May 2018) As a computing labs assistant, I helped undergraduate students with their java labs e.g. logic development, syntax correction and debugging of code.

• Internship in CERN, Geneva Switzerland (Jun 2014 -Aug 2014)
During this internship, I worked on a Project related to Compact Muon Solenoid (CMS) detector. My project was stability analysis of the gaseous Muon detector being used in CMS. In this project, I used ROOT software and C++ for plotting different graphs and histograms, for stability analysis.


EDUCATION

MASTERS DEGREE BY RESEARCH IN COMPUTING (January 2017 – January 2019)
Technological University Dublin , Tallaght campus Ireland
As part of this masters, I worked on a fully funded project based on FPGAs in collaboration with Xilinx research labs Ireland. I am exploring the implementation of computer vision algorithms on FPGA for accelerated execution. I used C/C++, python, TCL and Verilog for development of SOC applications.


B.S ELECTRICAL ENGINEERING (with specialization in Electronics) (October 2010 - June 2014)
Pakistan Institute of Engineering and Applied Sciences, Nilore Islamabad
CGPA: 3.98/4.0 (Gold Medalist)
Final year project: Implementation of Recursive Least Squares (RLS) Algorithm on FPGA for Brain
Imaging (Funded by National ICT R&D Fund).

Global- UGRAD Exchange Program (August 2012 – December 2012)

Saginaw Valley State University, Michigan U.S.A. CGPA: 4.0/4.0 (Nominated for President’s List)


PUBLICATIONS

• “Real-time brain activation detection by FPGA implemented adaptive algorithm “(Presented in IEEE
International Conference on Innovations in Electrical and Computational Technologies 2017).

• “Implementation of a Scalable Real Time Canny Edge Detector on Programmable SOC”. (Presented
in IEEE International Conference on Electrical and Computing Technologies and Applications, 2017).



ACHIEVEMENTS & AWARDS
• Awarded President’s research award by Institute of Technology, Tallaght to pursue Master’s degree by research (2017).
• Awarded the PIEAS Gold Medal for graduation as 1st position holder of my Batch. (2016)
• Received appreciation certificate from Federal Minister of Petroleum for my outstanding work in commissioning of Rehman Production Facility, PGNiG Pakistan Branch. (2015)
• Winner of the competition Race to innovation in National Electronics Olympiad, Giki (2013).
• Winner in the Mathemagician and Coding race in IEEE-Week held in NU-FAST (2013).
• Nominated for PMNICTSP Success Story for outstanding performance as an ICT Scholar (2012).
• Spent a semester in Saginaw Valley State University, Michigan U.S.A as full-time student and
Cultural Ambassador of Pakistan. (2012)
• Qualified for President List in Saginaw Valley State University, Michigan U.S.A for securing a
C.G.P.A of 4.0 on scale of 4.0. (2012)
• Nominated as “Student of the month” by Saginaw Valley State University, Michigan U.S.A. (2012)
• Invited as speaker, by Office of International programs Saginaw Valley State University Michigan
U.S.A, during International Education Week. (2012).
• Recipient of ICT scholarship From Govt. of Pakistan for Bachelor’s degree (2010).


CO-CURRICULAR ACTIVITIES

• Management Head and Secretary IEEE PIEAS Student Branch (Apr 2013-May 2014) Being the management Head and Secretary of student branch I organized and managed different competitions like Race to innovation, Programmer-X etc. and workshops on Microcontrollers, Matlab etc. to enhance the technical capabilities of students in the field of electrical engineering.

• Cultural Ambassador of Pakistan in USA (Aug 2012- Dec 2012)
Being the cultural ambassador of Pakistan I delivered presentations on Pakistan in international student club, international education week and optimist club. I also participated in Americans festivals like Thanksgiving, Halloween and learnt about their culture and shared my culture with them.

TECHNICAL SKILLS

• Familiarity with Programming languages such as Python, R, Java, C, C++, Verilog, VHDL
• Familiarity with softwares and systems like Genus, Design Compiler ,Spyglass, Tessent, Tempus, Quessta, Questa CDC, Questa verify, Incisive, Conformal LEC, MS Office, MATLAB, Simulink, , ModelSim, Vivado, Vivado HLS, Windows and Linux.