My classes will be ranging from beginning concepts of computer architecture from von neumann model to advanced super-scalar server architecture; I can also teach multi-core architecture and very proficient in cache coherency and consistency models and prep the students for industry standard skills. Ideal students would be under-graduate students looking for a career in Hardware companies like ARM, intel etc. I can do excellent interview prep too!
I am currently doing my PhD in memory consistency and coherency models- I love anything related to computer architecture- very proficient in C/C++. Computer Architecture is the intersection of Hardware and Software and a very exciting field open to anyone with a bit of curiosity!
(concealed information) | 32 Moatwood Green, Welwyn Garden City- AL73SN | +(concealed information)96 | (concealed information)
EDUCATION PhD in Computer Engineering: May-2022 (expected)
North Carolina State University, USA
B.E (Hons) Electronics and Instrumentation: May-2011
Birla Institute of Technology and Science, Pilani, India
Computer Design and Technology, Architecture of Parallel Computers, Code Generation and Optimization (Compilers), Digital ASIC Design,
Advanced Microarchitecture, Operating Systems Principles, GPU Architecture (GPGPUs), Computer Networks, Embedded Systems, Quantum
1. Designed a cycle simulator for Dynamic Instruction Scheduling in out-of-order Superscalar Processor using C++; features included
multi-functional execution units, configurable scheduler and superscalar widths. Further, Simulated Trace processor micro-architecture
with Control Independence optimization unit on a detailed C++ superscalar functional simulator.
2. Designed a Simulator for a Multilevel Cache in C++ with WBWA, WTNA write policies and LRU replacement policy . Used the generic
Cache module to have Victim cache for L1 Cache. Further enhanced this Cache module to implement bus based Cache Coherence
Protocols (MSI, MESI, MOESI, Dragon) in a Symmetric Multiprocessor (SMP)-like environment with L2 as shared cache .
3. Simulated a configurable branch predictor with BTB for Bimodal, Gshare and Hybrid predictors and analyzed for various configurations.
Compiler Optimizations (used LLVM IR): Implemented an LLVM bitcode generator for a subset of the C language using LLVM C APIs. Also,
implemented libraries to perform Common Sub-Expression Elimination (CSE), Dead Code Elimination (DCE), Loop Invariant Code Motion
(LICM) optimization passes, to gather vital statistics of an LLVM module and to identify SIMD Vectorization opportunities in LLVM IR.
Arm Holdings, Cambridge, UK : Apr-2020 to June-2020, 3mons
Areas of work: Explored various consistency models; understood ARM-TME’s transactional model and tried to add support for the same on a
custom memory-model-validation-tool developed in-house using functional programming.
Arm Holdings, Cambridge, UK: June-2019 to Aug-2019, 3mons
Areas of work: Created a framework for workload characterization for the SVOS team. Started a setup to analyze the payloads used within the
team to assess if they provided the right stresses for various validation purposes and proposed appropriate extensions to this setup.
Graphene Semiconductor Services Pvt Ltd, Bangalore, India: Apr-2014 to May-2015, 1yr 2mons
Member Technical Staff
Areas of work: On-site customer support to crucial customers like Qualcomm, Sandisk and Lantiq Communications (now Intel) as a Static Timing
Analysis expert. Activities involved driving timing closure of the chips, complete constraints development and verifications and provide CTS
strategies for PnR team.
Texas Instruments, Bangalore, India: June-2011 to Apr-2014, 2yrs 11mons
Areas of work: Worked on 28nm and 40nm technology nodes in various Physical Design and Static Timing Analysis roles. Ownership of the
design library for entire SoC team, PnR experiments for various Sub-blocks, Netlist to GDSII flow flush of a crucial test-chip and development of
timing constraints for various block/top level of the SoCs.
US PATENT: Placement aware clock gate cloning and fan-out optimization- number : 8,661,374
Programming: Tcl, Perl, Shell (bash/tcsh), Verilog, C, C++, OpenMP (API), CUDA. Tools: Synopsys PrimeTime, Synopsys Design Compiler,
Synopsys Talus and IC compiler, Mentor Graphics ModelSim, Apache RedHawk, GDB. OS: Linux and Windows
Perfect! Brilliant tutor who is able to explain concepts clearly and in a way which makes understanding them extremely easy! I would certainly recommend.
Perfect! Mahita is a really excellent and supportive tutor who goes out of her way to ensure that you comfortable and confident with the material being taught. She breaks things down into smaller components so that they are easier to understand and walks you through it step by step. I would highly recommend her!
Quick learner and grasps the concepts well. Focuses on learning more which is always great! Very prompt in communicating the requirements.
Just need a lot more practice to improve speed and skill for coding and debugging.
Explained high level concepts extremely well, as well as being very knowledgeable in her field. Helped me out tremendously with my own difficulties in university level computer science. Would highly recommend :)
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